Can in-memory computing be the key to next-generation AI chips?

 With the landing and large-scale application of artificial intelligence, AI chips have also become a common chip category. Compared with traditional chips, the main competitive advantage of AI chips lies in high computing power and high energy efficiency ratio. High computing power refers to the ability to complete AI calculations faster than traditional chips, while high energy efficiency ratio refers to the ability to complete calculations with less energy than traditional chips.

In the early days of the birth of AI chips, the AI chip architecture was mainly optimized for computing parallelism, thereby enhancing computing power.

At present, there are many players in global in-memory computing. A major problem with traditional in-memory computing is the contradiction between computing accuracy and application scenarios. If we want to solve this contradiction, we hope to have a low-power in-memory computing product for the mobile terminal, and its calculation accuracy can meet the calculation requirements of the mobile neural network (>4bit).

In-memory computing is a technology that straddles the two fields of devices and circuits. Usually, the interface between in-memory computing and digital circuits requires a lot of digital-to-analog conversion and signal driving, and these interfaces actually require a lot of circuit optimization work, otherwise It is easy to become the bottleneck of the overall performance. In order to solve this efficiency bottleneck, the development of large-scale resistive memory array drive technology can realize high-efficiency in-memory computing circuit interface; at the same time, it also paves the way for the scale of in-memory computing. The architectural level above the circuit also has its own unique instruction set technology.

In fact, compilers and instruction sets have always been important issues that plague the design of all artificial intelligence chips. The main problem that AI chips cannot truly exert their full computing power in practical applications is that the design of instruction sets and compilers is not good enough, resulting in chips that can only There is high computing power in the demo, but the efficiency drops significantly when the actual model provided by the user is running.

We have seen the rise of China's semiconductor industry, because publishing an article at a top semiconductor device conference like IEDM is itself an affirmation of related technologies. We hope to see more cases of high-tech semiconductor technology commercialization, and when there are many such dynamic high-tech semiconductor companies in the market, the spring of China's semiconductor industry will come.